A commonly used method for forming metal lines and vias is known as “damascene.” Generally, this method involves forming an opening in a dielectric layer, which separates the vertically spaced metallization layers. The opening is typically formed using conventional lithographic and etching techniques. After the formation, the opening is filled with copper or copper alloys. Excess copper on the surface of the dielectric layer is then removed by a chemical mechanical polish (CMP). The remaining copper or copper alloy forms vias and/or metal lines.
Copper is typically used for the damascene processes. Copper has a low resistivity, thus the RC delay caused by the resistance in the interconnect structure is low. However, with the down-scaling of the integrated circuits, the dimensions of copper interconnects are also down-scaled. When the dimensions of the copper interconnects approach the mean free path of electrons, the resistivity of the interconnect structure significantly increases. As a result, the RC delays caused by the interconnect structure significantly increase.
Various methods have been explored to reduce the resistivities of the interconnect structures. For example, diffusion barrier layers, which are used to prevent copper from diffusing into neighboring low-k dielectric layers, typically have high resistivities. Methods for forming thinner diffusion barrier layers are thus explored. However, in conventional diffusion barrier formation methods, the diffusion barrier layers exist at the via bottoms, causing the increase in the resistances of the interconnect structures. An additional problem is that with the increasing down-scaling of integrated circuits, the thickness of diffusion barrier layers becomes significant compared to the widths of the respective metal lines and vias. As a result, the formation of diffusion barrier layers and seed layers becomes increasingly difficult. Accordingly, new methods are needed to solve the above-discussed problems.